In a conventional placement and routing process of a semiconductor device, such as LSI, a connection through-hole (via) formed through an inter-layer insulating film for interconnecting an upper interconnect layer and a lower interconnect layer, is placed on a centerline of a line. FIG. 6 schematically shows the layout of vias in a conventional semiconductor device. The layout pattern of a via is usually represented by a square. As shown in FIG. 6, if the size of a via 103 is smaller than or equal to the line width of a conductor (metal) 101 provided in the lower layer, interconnection may be made without affecting a neighboring routing channel 104.
With recent progress of the miniaturization process in the manufacturing process for semiconductor devices and with the improvement in the interconnect technique and step coverage, a multi-layered interconnect structure has come to be used. In a semiconductor device of the multi-layered interconnect structure, the line width in the upper interconnect layer is usually larger than that in the lower interconnect layer. In this case, design references (design rules), such as an interconnect pitch in the lower interconnect layer to which the semiconductor miniaturization process is applied cannot be directly employed in producing the via for interconnecting the upper layer line and the lower layer line and hence the via size becomes larger than the line width in the lower interconnect layer.
Meanwhile, in a masterslice semiconductor integrated circuit, in which a routing channel lattice is formed on a basic gate cell and interconnect layers are formed extending along lattice lines of the routing channel lattice, there is known a semiconductor integrated circuit in which, even if there is a marked difference between the design reference of the basic cell process and the design process of the interconnection process, attempts are made to harmonize the design references to improve the integration density (see for example the Patent Publication 1). However, with this solution, the routing channel lattice is of a non-uniform pitch.
[Patent Document 1]
Japanese Patent Kokai Publication JP-A-10-56162 (page 7 and FIG. 5)